In a variety of transistor circuit applications--such as flat panel displays and time division multiplexed electronic telephone exchange equipment--complementary bipolar transistor devices are desirable that (1) are capable of handling high voltages (typically about 90 volt or more), (2) are integrated in separate single crystal silicon semiconductor regions of opposite bulk conductivity type, and (3) are mutually electrically isolated from one another by insulating dielectric isolation layers. These dielectric isolation layers have important advantages over pn junction isolation--such as enabling an overall more compact structure and hence a desirably greater device packing density, as well as resisting degradation of the electrical isolation caused by electron-hole pairs, including those pairs which are generated by external ionizing radiation. Other advantages of dielectric isolation over junction isolation include: (1) it eliminates unwanted latch-up action that could otherwise occur among pnpn structures inherently associated with the impurity diffusions of neighboring junction isolated devices, and (2) the dielectric isolation layer reduces the parasitic capacitances between the devices and the supporting substrate, as well as between the devices themselves, thereby enabling higher speed circuit operation.
In a variety of other circuit applications--such as circuits having a portion with high voltage handling capability for power switching and a low voltage portion (typically about 5 volts or less) for control circuitry--one or more high voltage handling transistors are desirable that are integrated in a single crystal silicon semiconductor region having a different uniform bulk conductivity or different bulk thickness (or both) from that of a separate single crystal silicon semiconductor region, the two regions being mutually electrically isolated from each other by insulating dielectric isolation layers.
K. E. Bean et al, in a paper entitled "Dielectric Isolation: Comprehensive, Current and Future," published in Journal of the Electrochemical Society: Reviews and News, Vol. 124, pp. 5C-12C (1977), describe a process for producing dielectrically isolated silicon crystal regions. All such regions, however, have the same uniform n type or p type conductivity as that of the original silicon body. Because of this resulting sameness of the conductivity of all regions, this process does not provide either the regions of the differing type of bulk conductivity desired for complementary bipolar transistor devices or the regions of differing magnitudes of bulk conductivity, or of different bulk thicknesses, as is desired for high voltage power switching circuitry combined with low voltage control circuitry.
In U.S. Pat. No. 4,393,573 entitled "Method of Manufacturing Semiconductor Device Provided With Complementary Semiconductor Elements," issued on July 19, 1983 to Kato et al, a process is described for making complementary high voltage devices with dielectric isolation. The process, however, involves the growth of epitaxial silicon upon a major surface of a silicon body both at a time when portions of the surface are coated with a masking layer of silicon nitride and/or silicon dioxide and at a time when portions of the surface are coated with portions of a layer of the dielectric isolation. Consequently the crystalline quality of the epitaxial silicon is not as high as needed for desirable performance of the transistor devices which are subsequently fabricated therein. It would therefore be desirable to have a process for forming dielectrically isolated semiconductor regions of differing properties (bulk conductivity type and/or magnitude, and/or bulk thickness) which mitigates the shortcomings of prior art.